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data sheet ics87946ayi-147 revision a august 7, 2009 1 ?2009 integrated device technology, inc. low skew, 1, 2 lvcmos/lvttl clock generator ics87946i-147 general description the ics87946i-147 is a low skew, 1, 2 lvcmos/lvttl clock generator and a member of the hiperclocks? family of high performance clock solutions from idt. the ics87946i-147 has two selectable single ended clock inputs. the single ended clock inputs accept lvcmos or lvttl input levels. the low impedance lvcmos/lvttl outputs are designed to drive 50 ? series or parallel terminated transmission lines. the effective fanout can be increased from 10 to 20 by utilizing the abilit y of the outputs to drive two series terminated lines. the divide select inputs, div_selx, control the output frequency of each bank. the outputs can be utilized in the 1, 2 or a combination of 1 and 2 modes. the master reset input, mr/noe, resets the internal frequency dividers and also controls the active and high impedance stat es of all outputs. the ics87946i-147 is characterized at full 3.3v for input v dd, and mixed 3.3v and 2.5v for output operating supply mode. guaranteed bank, output and part-to-part sk ew characteristics make the ics87946i-147 ideal for those clock distribution applications demanding well defined performance and repeatability. features ? ten single ended lvcmos/lvttl outputs, 7 ? typical output impedance ? selectable lvcmos/lvttl clk0 and clk1 inputs ? clk0 and clk1 can accept the following input levels: lvcmos and lvttl ? maximum input frequency: 250mhz ? bank skew: 30ps (maximum) ? output skew: 175ps (maximum) ? part-to-part skew: 850ps (maximum) ? multiple frequency skew: 200ps (maximum) ? 3.3v core, 3.3v or 2.5v output supply modes ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 clk_sel v dd clk0 clk1 div_sela div_selb div_selc gnd gnd qb0 v ddb qb1 gnd qb2 v ddb v ddc v ddc qc0 gnd qc1 v ddc qc2 gnd qc3 gnd qa0 v dda qa1 gnd qa2 v dda mr/noe ics87946i-147 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view pin assignment block diagram clk0 clk_sel clk1 div_sela qa[0:2] 0 1 0 1 1 2 pullup pullup pullup pulldown pulldown div_selb div_selc qc[0:3] 0 1 pulldown mr/noe pulldown qb[0:2] 0 1 0 1 pulldown 3 3 4
ics87946ayi-147 revision a august 7, 2009 2 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 clk_sel input pulldown clock select input. when high, selects clk1. when low, selects clk0. lvcm os / lvttl interface levels. 2v dd power positive supply pin. 3, 4 clk0, clk1 input pullup single-ended clock inputs. lvcmos/lvttl interface levels. 5 div_sela input pulldown controls frequency division for bank a outputs. see table 3 lvcmos/lvttl interface levels. 6 div_selb input pulldown controls frequency division for bank b outputs. see table 3. lvcmos/lvttl interface levels. 7 div_selc input pulldown controls frequency division for bank c outputs. see table 3. lvcmos/lvttl interface levels. 8, 11, 15, 20, 24, 27, 31 gnd power power supply ground. 9, 13, 17 v ddc power output supply pins for bank c outputs. 10, 12, 14, 16 qc0, qc1, qc2, qc3 output single-ended bank c clock outputs. lvcmos/lvttl interface levels. 7 ? typical output impedance. 18, 22 v ddb power output supply pins for bank b outputs. 19, 21, 23 qb2, qb1, qb0 output single-ended bank b clock outputs. lvcmos/lvttl interface levels. 7 ? typical output impedance. 25, 29 v dda power output supply pins for bank a outputs. 26, 28, 30 qa2, qa1, qa0 output single-ended bank a clock outputs. lvcmos/lvttl interface levels. 7 ? typical output impedance. 32 mr/noe input pulldown active high master reset. active low output enable. when logic high, the internal dividers are reset and the outputs are (high-impedance). when logic low, the internal dividers and the outputs are enabled. see table 3. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance v dd = v dda = v ddb = v ddc = 3.6v 25 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance 7 ?
ics87946ayi-147 revision a august 7, 2009 3 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator function tables table 3. clock input function table absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v dda = v ddb = v ddc = 3.3v 0.3v, t a = -40c to 85c inputs outputs mr/noe div_sela div_selb div_ selc qa0:qa2 qb0:qb2 qc0:qc3 1 x x x high-impedance high-impedance high-impedance 00xx f in /1 active active 01xx f in /2 active active 0x0x active f in /1 active 0x1x active f in /2 active 0 x x 0 active active f in /1 0 x x 1 active active f in /2 item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddx + 0.5v package thermal impedance, ja 47.9 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.0 3.3 3.6 v v dda, v ddb, v ddc output supply voltage 3.0 3.3 3.6 v i dd power supply current 55 ma i dda , i ddb , i ddc output supply current 23 ma
ics87946ayi-147 revision a august 7, 2009 4 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator table 4b. power supply dc characteristics, v dd = 3.3v 5%, v dda = v ddb = v ddc = 2.5v 5%, t a = -40c to 85c table 4c. lvcmos/lvttl dc characteristics, v dd = v dda = v ddb = v ddc = 3.3v 0.3v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddx /2. see parameter measurement information section. load test circuit diagrams. symbol parameter test conditio ns minimum typi cal maximum units v dd positive supply voltage 3.135 3.3 3.465 v v dda, v ddb, v ddc output supply voltage 2.375 2.5 2.625 v i dd power supply current 55 ma i dda , i ddb , i ddc output supply current 22 ma symbol parameter test conditi ons minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage mr/noe, div_sela, div_selb, div_selc, clk_sel -0.3 0.8 v clk0, clk1 -0.3 1.3 v i ih input high current mr/noe, div_sela, div_selb, div_selc, clk_sel v dd = v in = 3.6v 150 a clk0, clk1 v dd = v in = 3.6v 5 a i il input low current mr/noe, div_sela, div_selb, div_selc, clk_sel v dd = 3.6v, v in = 0v -5 a clk0, clk1 v dd = 3.6v, v in = 0v -150 a v oh output high voltage; note 1 v dda = v ddb = v ddc = 3.6v 2.6 v v ol output low voltage; note 1 v dda = v ddb = v ddc = 3.63v 0.5 v i ozl output hi-z current low v dda = v ddb = v ddc = 3.63v -5 a i ozh output hi-z current high v dda = v ddb = v ddc = 3.63v 5 a
ics87946ayi-147 revision a august 7, 2009 5 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator table 4d. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, v dda = v ddb = v ddc = 2.5v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v ddx /2. see parameter measurement information section. load test circuit diagrams. symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage mr/noe, div_sela, div_selb, div_selc, clk_sel -0.3 0.8 v clk0, clk1 -0.3 1.3 v i ih input high current mr/noe, div_sela, div_selb, div_selc, clk_sel v dd = v in = 3.465v 150 a clk0, clk1 v dd = v in = 3.465v 5 a i il input low current mr/noe, div_sela, div_selb, div_selc, clk_sel v dd = 3.465v, v in = 0v -5 a clk0, clk1 v dd = 3.465v, v in = 0v -150 a v oh output high voltage; note 1 v dda = v ddb = v ddc = 2.625v 1.8 v v ol output low voltage; note 1 v dda = v ddb = v ddc = 2.625v 0.5 v i ozl output hi-z current low v dda = v ddb = v ddc = 2.625v -5 a i ozh output hi-z current high v dda = v ddb = v ddc = 2.625v 5 a
ics87946ayi-147 revision a august 7, 2009 6 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator ac electrical characteristics table 5a. ac characteristics, v dd = v dda = v ddb = v ddc = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when th e device is mounted in a test socket with maintained trans verse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from v dd /2 of the input to v ddx /2 of the output. note 2: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 3: defined as skew across banks of outputs at the sa me supply voltage and with equal load conditions. measured at v ddx /2. note 4: defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. note 5: defined as skew between outputs on different devices operating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the outputs are measured at v ddx /2. note 6: these parameters are guaranteed by characterization. not tested in production. note 7: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units f max output frequency 250 mhz t pd propagation delay; note 1 ? 250mhz 2 5 ns t sk(b) bank skew, note 2, 7 measured on rising edge at v ddx /2 30 ps t sk(o) output skew; note 3, 7 measured on rising edge at v ddx /2 175 ps t sk(w) multiple frequency skew; note 4, 7 measured on rising edge at v ddx /2 275 ps t sk(pp) part-to-part skew; note 5, 7 measured on rising edge at v ddx /2 850 ps t r / t f output rise/fall time; note 6 20% to 80% 400 950 ps t pw output pulse width t period /2 - 1 t period /2 t period /2 + 1 % t en output enable time; note 6 ? = 1 0 m h z 3 n s t dis output disable time; note 6 ? = 1 0 m h z 3 n s
ics87946ayi-147 revision a august 7, 2009 7 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator table 5b. ac characteristics, v dd = 3.3v 5%, v dda = v ddb = v ddc = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device wi ll meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from v dd /2 of the input to v ddx /2 of the output. note 2: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 3: defined as skew across banks of outputs at the sa me supply voltage and with equal load conditions. measured at v ddx /2. note 4: defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. note 5: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the outputs are measured at v ddx /2. note 6: these parameters are guaranteed by characterization. not tested in production. note 7: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units f max output frequency 250 mhz t pd propagation delay; note 1 ? 250mhz 2 5 ns t sk(b) bank skew, note 2, 7 measured on rising edge at v ddx /2 35 ps t sk(o) output skew; note 3, 7 measured on rising edge at v ddx /2 175 ps t sk(w) multiple frequency skew; note 4, 7 measured on rising edge at v ddx /2 200 ps t sk(pp) part-to-part skew; note 5, 7 measured on rising edge at v ddx /2 875 ps t r / t f output rise/fall time; note 6 20% to 80% 400 950 ps t pw output pulse width t period /2 - 1 t period /2 t period /2 + 1 % t en output enable time; note 6 ? = 10mhz 3 ns t dis output disable time; note 6 ? = 10mhz 3 ns
ics87946ayi-147 revision a august 7, 2009 8 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator parameter measureme nt information 3.3v core/3.3v output load ac test circuit output skew bank skew 3.3v core/2.5v output load ac test circuit part-to-part skew multiple frequency skew scope qx lvcmos gnd 1.65v0.15v -1.65v0.15v v dd, v dda, v ddb, v ddc t sk(o) v ddo 2 v ddo 2 qx qy t sk(b) v ddx 2 v ddx 2 qx0:qxx qx0:qxx where x = bank a, b or c scope qx lvcmos gnd -1.25v 5% v dda, v ddb, v ddc v dd 1.25v 5% 2.05v 5% t sk(pp) v ddo 2 v ddo 2 part 1 part 2 qx qy tsk( ) qbx, qcx qax
ics87946ayi-147 revision a august 7, 2009 9 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator parameter measurement in formation, continued t pw & t period output rise/fall time propagation delay t pw t period v ddx 2 v ddx 2 v ddx 2 t pw t period odc = qax, qbx, qcx 20% 80% 80% 20% t r t f qax, qbx, qcx t pd v ddx 2 v ddx 2 clk0, clk1 qax, qbx, qcx
ics87946ayi-147 revision a august 7, 2009 10 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator application information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk inputs for applications not requiring the us e of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. o ut puts: lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. reliability information table 6. ja vs. air flow table for a 32 lead lqfp transistor count the transistor count for ics87946i-147 is: 1204 pin compatible to the mpc9446 and mpc946 ja vs. air flow linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
ics87946ayi-147 revision a august 7, 2009 11 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator package outline and package dimensions package outline - y suffix for 32 lead lqfp table 7. package dimensions for 32 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: bbc - hd all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.60 ref. e 0.80 basic l 0.45 0.60 0.75 0 7 ccc 0.10
ics87946ayi-147 revision a august 7, 2009 12 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-f ree configuration and are rohs compliant. part/order number marking package shipping packaging temperature 87946ayi-147 ics87946ai147 32 lead lqfp tray -40 c to 85 c 87946ayi-147t ics87946ai147 32 lead lqfp 1000 tape & reel -40 c to 85 c 87946AYI-147LF ics7946ai147l ?le ad-free? 32 lead lqfp tray -40 c to 85 c 87946AYI-147LFt ics7946ai147l ?lead-fr ee? 32 lead lqfp 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics87946ayi-147 revision a august 7, 2009 13 ?2009 integrated device technology, inc. ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator revision history sheet rev table page description of change date a t2 t8 1 2 8 10 12 features section added lead-free bullet. pin description table - corrected description for v dda , v ddb and v ddc . parameter measurement information section - added part-to-part skew, bank skew, and multiple frequency skew diagrams. application section - added recommendations for unused input and output pins. ordering information table - added lead-free marking. updated format throughout the datasheet. 7/22/08 a t5a - t5b t8 6 - 7 12 ac tables - added thermal note. ordering information table - corrected the part/order numbers and corrected the non-lf marking. updated header/footer of the datasheet. 8/7/09
ics87946i-147 data sheet low skew, 1, 2 lvcmos/lvttl clock generator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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